1. Field of the Invention
The present invention relates to a plasma display panel driving method, a plasma display panel driving circuit, and a plasma display device utilized in a flat TV, an information display, etc. and, more particularly to, a plasma display panel driving method, a plasma display panel driving circuit, and a plasma display device that are intended to reduce a data voltage.
2. Description of the Related Art
A plasma display panel (PDP) typically has many features such as a thin construction being free of flickering and having a large display contrast, a relatively large screen, a high response speed, being self-luminous type, and multiple-color emission by use of a luminant. Recently these features of the PDP qualify itself widely for use in various fields of a computer-related display device, a color image display, etc.
Those PDPs are classified by their operating method into an AC type that an electrode is covered by a dielectric to thereby indirectly operate the panel in an AC discharged state and a DC type that the electrode is exposed to a discharge space to thereby operate the panel in a DC discharged state. The AC type PDPs are further classified by their driving method into a memory operating type that utilizes a display cell memory and a refreshing type that does not utilize it. I should be noted, the luminance of the PDPs is proportional to the number of times of discharging operations. In the case of the refreshing type PDP, its luminance decreases with an increasing display capacity, so that this type of PDP is used mainly in a small display-capacity plasma display.
As shown in FIG. 13, the display cell comprises two insulating substrates 101 and 102 which are made of glass. The insulating substrate 101 provides a rear-side substrate and the insulating substrate 102, a front-side substrate.
On such a side surface of the insulating substrate 102 that faces the insulating substrate 101 are provided a transparent scanning electrode 103 and a transparent sustaining electrode 104. The scanning electrode 103 and the sustaining electrode 104 both extend in a horizontal direction (lateral direction) of the panel. On the scanning electrode and the sustaining electrode 104 are superposed trace electrode 105 and 106 respectively. These trace electrodes 105 and 106, which are made of a metal etc., are provided to decrease the electrode resistance between the electrodes 103 and 104 and an external driving device. Further, a dielectric layer 112 is provided to cover the scanning electrode 103 and the sustaining electrode 104, while a protecting layer 114 made of magnesium oxide etc. is provided to protect this dielectric layer 112 from discharge.
On such a side surface of the insulating substrate 101 that faces the insulating substrate 102 is provided a data electrode 107 which is perpendicular to the scanning electrode 103 and the sustaining electrode 104. The data electrode 107, therefore, extends in a vertical direction of the panel. Also, a partition 109 is provided to separate the display cells from each other horizontally. Also, a dielectric layer 113 is provided to cover the data electrode 107, while a phosphor layer 111 is formed on the sides of the partition 109 and the surface of the dielectric layer 113 to convert an ultraviolet ray generated by discharge of a gas into a visible light 110. In a space between the insulating substrates 101 and 102 is reserved a discharge gas space 108 by the partition 109, which discharge gas space 108 is filled with a discharge gas consisting of Helium, Neon, or Xenon or a gas mixture thereof.
As shown in FIG. 14 shows a block diagram of a conventional AC type plasma display. The PDP 1 comprises an n number (n: natural number) of row-directional scanning electrodes 3-1 through 3-n (103) and another n number of sustaining electrodes 4-1 through 4-n (104) which alternate with each other with a predetermined spacing therebetween and an m number (m: natural number) of column-directional (perpendicular to the scanning electrode and the sustaining electrode) data electrodes 10-1 through 10-m (107). The PDP 1, therefore, has an (n×m) number of display cells.
The conventional plasma display has such a circuit for driving the PDP1 that is comprised of a driving power source 21, a controller 22, a scan driver 23, a scanning pulse driver 24, a sustaining driver 25, and a data driver 26.
The driving power source 21 generates, for example, a logic voltage Vdd of 5V, a data voltage Vd of about 70V, and a sustaining voltage Vs of about 170V and also does it generate, based on the sustaining voltage Vs, a priming voltage Vp of about 400V, a scanning base voltage Vbw of about 100V, and a bias voltage Vsw of about 180V. The logic voltage Vdd is supplied to the controller 22, the data voltage Vd is supplied to the data driver 26, the sustaining voltage Vs is supplied to the scan driver 23 and the sustaining driver 25, the priming voltage Vp and the scanning base voltage Vbw are supplied to the scan driver 23, and the bias voltage Vsw is supplied to the sustaining driver 25.
The controller 22 is a circuit for generating, based on a video signal Sv supplied from the outside, scan driver control signals Sscd1-Sscd6, scanning pulse driver control signals Sspd11-Sscd1n and Sspd21-Sspd2n, sustaining driver control signals Ssud1-Ssud3, the data driver control signals Sdd11-Sdd1m and Sdd21-Sdd2m. The scan driver control signals Sscd1-Sscd6 are supplied to the scan driver 23, the scanning pulse driver control signals Sspd11-Sspd1n and Sspd21-Sspd2n are supplied to the scanning pulse driver 24, the sustaining driver control signals Ssud1-Ssud3 are supplied to the sustaining driver 25, and the data driver control signals Sdd11-Sdd1m and Sdd21-Sdd2m are supplied to the data driver 26.
As shown in FIG. 15, the scan driver 23 is comprised of, for example, six switches 23-1 through 23-6. To one end of the switch 23-1 is applied the priming voltage Vp, and the other end thereof is connected to a positive line 27. To one end of the switch 23-2 is applied the sustaining voltage Vs, and the other end thereof is connected to positive line 27. To one end of the switch 23-3 is grounded, and the other end thereof is connected to an negative line 28. To one end of the switch 23-4 is applied the scanning base voltage Vbw, and the other end thereof is connected to the negative line 28. The switch 23-5 has its one end grounded and the other end connected to the positive line 27. The switch 23-6 has its one end grounded and the other end connected to the negative line 28. The switches 23-1 through 23-6 are turned ON/OFF by the scan driver control signals Sscd1 through Sscd6 respectively, to supply a voltage having a predetermined waveform to the scanning pulse driver 24 through the positive line 27 and the negative line 28.
As shown in FIG. 15, the scanning pulse driver 24 is comprised of, for example, an n number of switches 24-11 through 24-1n, an n number of switches 24-21 through 24-2n, an n number of diodes 24-31 through 24-3n, and an n number of diodes 24-41 through 24-4n. The diodes 24-31 through 24-3n are connected parallel between the ends of the switches 24-11 through 24-ln respectively, while the diodes 24-41 through 24-4n are connected parallel between the ends of the switches 24-21 through 24-2n respectively. Also, the switches 24-1a (a: natural number not larger than n) and the switch 24-2a are interconnected in cascade, the other ends of the switches 24-11 through 24-ln are commonly connected to the negative line 28, and the other ends of the switches 24-21 through 24-2n are commonly connected to the positive line 27. Further, an interconnection of the switches 24-1a and 24-2a is connected to a scanning electrode 3-a which is disposed at the a′th row counting from the top of the PDP1. The switches 24-11 through 24-1n and the switches 24-21 through 24-2n are turned ON/OFF by the scanning pulse driver control signals Sspd11 through Sspd1n and Sspd21 through Sspd2n to sequentially supply voltages Psc1 through Pscn of respectively predetermined waveforms to the scanning electrodes 3-1 through 3-n, respectively.
As shown in FIG. 16, the sustaining driver 25 is comprised of, for example, three switches 25-1 through 25-3. To one end of the switch 25-1 is applied the sustaining voltage Vs and to the other end thereof, connected the sustaining electrodes 4-1 through 4-n commonly. One end of the switch 25-2 is grounded and, to the other end thereof is connected the sustaining electrodes 4-1 through 4-n commonly. To one end of the switch 25-3 is applied the bias voltage vsw and to the other end thereof are connected the sustaining electrodes 4-1 through 4-n commonly (see FIG. 14). The switches 25-1 through 25-3 are turned ON/OFF by the sustaining driver control signals Ssud1 through Ssud3 to simultaneously supply a voltage Psu of a predetermined waveform to the sustaining electrodes 4-1 through 4-n.
As shown in FIG. 17, the data driver 26 is comprised of, for example, an m number of switches 26-11 through 26-1m, an m number of switches 26-21 through 26-2m, an m number of diodes 26-31 through 26-3m, and an m number of diodes 26-41 through 26-4m. The diodes 26-31 through 26-3m are connected parallel between the ends of the switches 26-21 through 26-2m respectively, while the diodes 26-41 through 26-4m are connected parallel between the ends of the switches 26-21 through 26-2m. The switches 26-1b (b: natural number not larger than m) and the switch 26-2b are connected in cascade, the other ends of the switches 26-11 through 26-1m are commonly grounded, and to the other ends of the switches 26-21 through 26-2m is supplied the data voltage Vd. Further, an interconnection of the switches 26-1b and 26-2b is connected to the data electrode 10-b which is disposed at the b′th column counting from the leftmost of the PDP 1. The switches 26-11 through 26-1m and the switches 26-21 through 26-2m are turned ON/OFF by the data driver control signals Sdd11 through Sdd1m and Sdd21 though Sdd2m to sequentially supply voltages Pd1 through Pdm of respective predetermined waveforms to the data electrodes 10-1 through 10-m, respectively.
The following will describe the write-in selection type driving operations of the conventional plasma display having the above configuration. FIG. 18 shows a timing chart of the write-in selection type driving operations of the conventional plasma display. As shown in FIG. 18, the write-in selection type driving operations employ a sub-field method, by which each sub-field is provided with four sequentially preset periods of a priming period Tp, an address period Ta, a sustaining period Ts, and a charge erasure period Te. It is hereinafter supposed that a reference voltage of the scanning and sustaining electrodes is called a sustaining voltage Vs, a higher voltage is called a positive polarity voltage, and a lower voltage is called a negative polarity voltage. Also, a reference voltage of the data electrode is called a ground potential GND, a higher voltage is called a positive polarity voltage, and a lower voltage is called a negative polarity voltage.
During the priming period Tp, first the external video signal Sv is supplied to the controller 22, which then starts to generate the scan driver control signals Sscd1-Sscd6, the sustaining driver control signals Ssud1-Ssud3, and the scanning pulse driver control signals Sspd11-Sspd1n and Sspd21-Sspd2n and also does it start to generate the data driver control signals Sdd11-Sdd1m having a level based on the video signal Sv and the data driver control signals Sdd21-Sdd2m of a low level, and then supplies these control signals to the predetermined drivers.
As a result, during the priming period Tp, the high-level scan driver control signal Sscd1 turns ON the switch 23-1, while the high-level sustaining signal Ssud2 turns ON the switch 25-2. As shown in FIG. 18, therefore, to all of the scanning electrodes 3-1 through 3-n is applied a positive-polarity priming pulse Pprp, while to all of the sustaining electrodes 4-1 through 4-n is applied a negative-polarity priming pulse Pprn. This causes priming discharge generated to occur, at every display cell, in the discharge gas space near an inter-electrode gap between the scanning electrode 103 (3-1 through 3-n) and the sustaining electrode 104 (4-1 through 4-n). With this, an active particle liable to generate write-in discharge at the display cell is generated in the discharged gas space 108, negative wall charge sticks to the scanning electrodes 3-1 through 3-n, positive wall charge sticks to the sustaining electrodes 4-1 through 4-n, and positive wall charge sticks to the data electrodes 10-1 through 10-m.
Next, the sustaining driver control signal Ssud2 falls to the LOW level to turn OFF the switch 25-2, while at the same time the sustaining driver signal Ssud1 rises to the HIGH level to turn ON the switch 25-1. Then, the scan driver control signal Sscd2 falls to turn OFF the switch 23-2, while at the same time the scan driver control signal Sscd3 rises to turn ON the switch 23-3. As a result, therefore, after all of the sustaining electrodes 4-1 through 4-n are held at the sustaining voltage Vs of about 170V, the priming erasure pulse Ppre is applied to all of the scanning electrodes 3-1 through 3-n. This causes weak discharge to occur at every display cell. This decreases the amounts of negative wall charge on the scanning electrodes 3-1 through 3-n, positive wall charge on the sustaining electrodes 4-1 through 4-n, and positive wall charge on the data electrodes 10-1 through 10-m.
Next, in the initial state of the address period Ta, the switch 25-3 is held ON by the high-level sustaining driver control signal Ssud3 and the switches 23-4 and 23-5 are also held ON by the high-level scan driver control signals Sscd4 and Sscd5 supplied in the latter half of the priming period Tp. To all of the sustaining electrodes 4-1 through 4-n is applied the positive polarity (bias voltage Vsw) bias pulse Pbp and also the pulses Psc1-Pscn applied to all the scanning electrodes 3-1 through 3-n are once held at the scanning base voltage Vbw in potential.
In such a state, the scanning pulse driver control signals Sspd11-Sspd1n fall to the LOW level sequentially and, correspondingly, the scanning pulse driver control signals Sspd21-Sspd2n rise to the HIGH level sequentially, thus turn OFF the switches 24-11 through 24-1n sequentially and also turn ON the switches 24-21 through 24-2n sequentially. Further, in synchronization therewith, although not shown, the data driver control signals Sdd11-Sdd1m rise to the HIGH level owing to the video signal Sv, matching which the data driver control signals Sdd21-Sdd2m rise to thereby cause the video signal Sv to turn ON the switches 26-11 through 26-1m and turn OFF the switches 26-21 through 26-2m. With this, when data is written to a displace cell in the a′th row in the b′th column, the negative-polarity scanning pulse Pwsn is applied to the scanning electrode 3-a, while at the same time the positive-polarity data pulse Pdb is applied to the data electrode 10-b in the b′th column. As a result, opposed discharge occurs at the display cell in the a′th row in the b′th column and also triggers off surface discharge as write-in discharge between the scanning electrode and the sustaining electrode, thus sticking wall charge to the electrodes. The display cells at which the write-in discharge did not occur remain in such a state that it has less wall charge stuck thereto after the charge is erased during the priming period Ta.
Next, in the sustaining period Ts, the scan driver control signals Sscd2 and Sscd6 alternately rise and fall repeatedly by as many times as according to their respective sub-fields. As a result, the switches 23-3 and 23-6 are alternately turned ON and OFF repeatedly. In synchronization therewith, the sustaining driver control signals Ssud1 and Ssud2 alternately rise and fall as many time as according to their respective sub-fields. As a result, the switches 25-1 and 25-2 are alternately turned ON and OFF repeatedly. Therefore, to all of the scanning electrodes 3-1 through 3-n is applied the negative-polarity sustaining pulse Psun1 as many times as according to the sub-field, while at the same time, to all of the sustaining electrodes 4-1 through 4-n is applied the negative-polarity sustaining pulse Psun2 as many times as according to the sub-field exclusively against the sustaining pulse Psun1. This causes the display cells to which no write-in operation was performed during the address period Ta to have an extremely small amount of wall charge, so that even if the sustaining pulse is applied to any one of these display cells, the sustaining discharge will not occur there. The display cell at which the write-in discharge occurred during the address period Ta, on the other hand, has positive charge stuck to its scanning electrode and negative charge stuck to its sustaining electrode, so that the sustaining pulse and the wall charge voltage are superimposed on each other to thereby raise a voltage across the electrodes in excess of a discharge start voltage, thus giving rise to discharge.
Next, during the charge erasure period Te, the scan driver control signal Sscd3 rises to thereby turn ON the switch 23-3. As a result, the negative-polarity charge erasure pulse Peen is applied to all of the scanning electrodes 3-1 through 3-n. At all of the display cells, therefore, weak discharge occurs. This causes the wall charge accumulated at the scanning electrode and the sustaining electrodes in the display cells that were emitting light during the sustaining period Ts to be erased, thus unifying the charged state of all the display cells.
In contrast to this driving method, there is available such a driving method that intends to eliminate the priming period. Hereinafter, the driving method shown in FIG. 18 is called a first prior art example and that for eliminating the priming period is called a second prior art example. FIG. 19. shows a timing chart of driving method of the second prior art.
As shown in FIG. 19, in the second prior art example, the scanning base voltage Vbw is set at a negative potential, the sustaining electrode's bias level Va and scanning base voltage Vsw during the priming period Tp are set lower in potential than the sustaining voltage Vs, the final arrival potential of the priming erasure pulse Ppre is set higher than the scanning pulse Pwsn in potential.
Also, such a driving method is proposed that reduces the potential amplitude of the data pulse by setting the potential of the sustaining electrode while the priming erasure pulse Ppre is applied to the scanning electrode higher than the potential of the sustaining electrode while the scanning pulse Pwsn is applied to the sustaining electrode (see Japan Patent Publication No. 2000-305510). Hereinafter, this driving method is called a third prior art example. FIG. 20 shows a timing chart of driving method of third prior art.
As shown in FIG. 20, in the third prior art example, like with the first prior art example, the potentials of the scanning electrode and the sustaining electrode are set not less than 0V always. Also, the bias level Va of the sustaining electrode while the priming erasure pulse Ppre is applied to the scanning electrode is set higher by 0-40V than the scanning base voltage Vsw of the sustaining electrode during the address period Ta. Correspondingly, the final arrival potential of the priming erasure pulse Ppre is set higher than the potential GND of the scanning pulse Pswn by 0-40V.
The first prior art example, however, has larger power consumption, thus suffering from a problem that it cannot meet the recent low power consumption requirement. The second prior art example, on the other hand, has the scanning electrode's potential held at a negative value during the address period Ta, thus suffering from a problem of a complicated power source construction and an insufficient decrease in power consumption. Further, the third prior art example has the potential of the sustaining electrode while the priming erasure pulse Ppre is applied to the scanning electrode set higher than the value thereof during the address period Ta, to excessively reduce the wall charge on the scanning electrode and the sustaining electrode, thus suffering from a problem of difficulty in generation of write-in discharge and deterioration in driving characteristics.